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Live Q&A - Hardware Security Analysis on Soft-Core RISC-V Processors

Colin O'Flynn - Watch Now - Duration: 33:45

Live Q&A - Hardware Security Analysis on Soft-Core RISC-V Processors
Colin O'Flynn
Live Q&A with Colin O'Flynn for the talk titled Hardware Security Analysis on Soft-Core RISC-V Processors
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No comments or questions yet. Will you be the one who will break the ice?

15:41:35	 From  BobF : These hacking techniques (side channel, glitching attacks) all rely on real physical connection to pcb tracks/pins. Surely, what’s necessary is for comprehensive and continuous pin (track) monitoring that detects anomaly loading and subsequently, stops safe. Or am I barking up the wrong tree?
15:47:53	 From  BobF : Non-contact, admittedly, requires other solutions.
15:53:47	 From  BobF : Solutions that do not need epoxy encapsulation / shielding to prevent i.e. solid-state solutions
15:58:44	 From  Michael Kirkhart : chatgpt, make me a aes instruction for a RISCV processor?
15:59:00	 From  BobF : Why roman character for 5 ? Thought I'll just throw it in ... can we expect RISC-X, RISC-C, RISC-M?
16:00:10	 From  BobF : Plenty of room for upgrades !
16:00:19	 From  Colin O'Flynn (NewAE) : 😁
16:02:25	 From  Vishwa Perera : Reacted to "{9645D430-6716-4766-823B-676D026AC816}.png" with 👍
16:02:27	 From  George Addison : That's chatGPT, so it sounds confident, I don't know if it's right

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