Using RPI Pico for testing your FPGA Application

Developing any FPGA or Embedded system can be complex, especially when it comes to validating either on development boards or in the real system that it functions as intended across all operating and failure conditions.

This is especially true when we are working with high reliability or mission critical systems such as satellite applications where we might want to retire functional risk early in the development program.

In this session we will explore how we can use RPI Pico to emulate system interfaces connected to our embedded system / FPGA. This allows the emulation of failure conditions, boundary conditions and corner cases with ease. Implementing such an approach will assist with validation and reduce the risks of issues later in development.

We will present several real-world examples where Adiuvo has used RPI Pico to simulate interfaces from SPI and I2C to clocking and advanced communication interfaces like SpaceWire. 

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Live Q&A - Using RPI Pico for testing your FPGA Application

Live Q&A with Adam Taylor for the talk titled Using RPI Pico for testing your FPGA Application

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Why your FPGA Design Might Need a Softcore Processor – What are the Options ?

FPGA are great for implementing highly parallel structures for image, signal, data processing and algorithms. These structures are ideal for implementation in programmable logic however, the control, configuration, interfacing and man machine interfacing require more often than not sequential processing. Of course for simple applications Finite State Machines can be used however designing, modifying and maintain which makes the difficult to implement complex control structures. The solution is to implement a simple soft core processor in the FPGA, this session will explore what our processor choices are proprietary vs open source, the decision matrix for implementation and trade-offs which occur when we decide to include the softcore processor in the FPGA.

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Live Q&A - Why your FPGA Design Might Need a Softcore Processor – What are the Options ?

Live Q&A with Adam Taylor for the talk titled Why your FPGA Design Might Need a Softcore Processor – What are the Options ?

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Building Accelerated Applications with Vitis

Do you want to benefit from the acceleration of programmable logic using C or C++, for your quantitative finance /  signal or image processing or AI/ML applications.  The Vitis Unified Software Platform enables developers to more easily tap into the benefits of Xilinx heterogeneous SoCs and accelerate their applications, without needing advanced hardware development knowledge. This workshop will provide an in-depth tutorial on how to get started with Vitis and Vitis AI.

Topics covered in this workshop include:

• Vitis features and elements
• Vitis libraries
• OpenCL
• Vitis development flows
• Optimizing software for programmable logic implementation
• Vitis AI for machine learning inference acceleration
• …and more!

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Live Q&A - Building Accelerated Applications with Vitis

Live Q&A with Adam Taylor for the workshop talk titled Building Accelerated Applications with Vitis

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PYNQ: Using FPGA to Accelerate Python applications (2020)

PYNQ is an open source Python framework from Xilinx which enables Python developers to access the performance provided by programmable logic, traditionally in the realm of electronic engineers. Being able to access programmable logic from Python brings with it acceleration factors of 10x, 100x and beyond to applications. This session will introduce the PYNQ framework, before demonstrating a number of image processing and machine learning applications developed using the PYNQ framework, showcasing not only the performance boost but also the ease of use.

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