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Zynq ® Ultrascale+™ delivers Deterministic Processing for Mixed Criticality Applications in Industrial, Automotive, and Aviation Markets

Dr. Giulio Corradi - Watch Now

Today's market requirements are forcing increased computational requirements across all embedded applications through the use of multi-core SoCs, while simultaneously requiring the preservation of legacy real-time code often developed decades ago for single core processors. Often, the performance limitations of real-time processors lead designers to consider and use application processors to achieve desired performance at expense of determinism and worst case execution time (WCET). This webinar describes how to use the ARM Cortex® A53 application processor cluster in Zynq® Ultrascale+™ to implement real-time asymmetric multiprocessing (RTAMP). This approach results in improving worst case execution time (WCET) and reducing latency by isolating and partitioning the cluster such that software developed for single cores can be reused. Demand for this solution is has skyrocketed in Industrial, Automotive and Avionics applications because software architects strongly prefer to use an application processing cluster like a set of single cores when executing real time code. Shared resources like the level 2 cache and memory controller guarantee performances on average, however worst case execution time is affected by interference amongst cores when accessing shared caches and memories. The combination of programmable logic technology and coloured lockdown concepts for shared cache management in conjunction with the open-source Jailhouse hypervisor make it possible to use Linux and bare-metal isolated applications running independently in the cluster. The overhead introduced by a hypervisor is also reduced, making the overall approach very lean.

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HR
Score: 0 | 5 months ago | no reply

Hi,
Thanks for the talk! Is there a way to use hypervisors without having to boot to linux at first? Or how do you ensure that the real-time tasks survive error conditions in the proposed setup?

EC_User_001_JP
Score: 0 | 5 months ago | no reply

Is the DDR controller for ZU3/4 SoC - ASIL certified? Ex: If we are using the shared bus between Safety core and non safety core - is there any protection mechanisms to detect data corruption or unauthorized access to certain memory addresses at run time?

EC_User_001_JP
Score: 0 | 5 months ago | no reply

Hello Dr. Giulio - Is it possible to know if ZU3/ZU4 Ultrascale SoC - have any ISO26262 specific certification? I would like to know more about its use in the Automotive Safety use case - and particularly on its runtime protection features (MPU) for RAM.

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