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What the FAQ is an FPGA

Presented by Clive "Max" Maxfield

A lot of people design embedded systems. Some of them are the hardware design engineers who create the boards. Others are the software developers who program the boards. The one thing that most of them have in common (apart from mutual distrust of each other) is that they predominantly use microcontrollers (MCUs) as the primary processing element in their designs.

Most of them have heard of FPGAs, but all they typically know is that these devices can be programmed to perform different functions -- they don't know how. Similarly, most of them have heard about languages like Verilog and VHDL, but all they typically know is that FPGA designers use these languages to capture the design -- they don't know how these hardware description languages (HDLs) differ from programming languages like C/C++.

In this presentation, engineer, writer, and communicator Max The Magnificent (a legend in his own lunchtime) will rend the veils asunder and reveal all. Max says that we will be leaping from topic to topic with the agility of young mountain goats, so he urges attendees to dress appropriately.

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PYNQ: Using FPGA to Accelerate Python applications

Presented by Adam Taylor

PYNQ is an open source Python framework from Xilinx which enables Python developers to access the performance provided by programmable logic, traditionally in the realm of electronic engineers. Being able to access programmable logic from Python brings with it acceleration factors of 10x, 100x and beyond to applications. This session will introduce the PYNQ framework, before demonstrating a number of image processing and machine learning applications developed using the PYNQ framework, showcasing not only the performance boost but also the ease of use.

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Does the Future of High-Level Synthesis Belong to Python?

Presented by Jason Pecor

The Python programming language continues to grow in popularity and momentum crossing diverse application boundaries such as web development, data science, artificial intelligence, and - thanks to MicroPython and CircuitPython - micro-controller based embedded systems. More and more engineers are adopting this powerful and flexible language putting it to work for intensive processing use cases.

C and C-based derivatives have traditionally served as the primary language used for high-level FPGA synthesis flows. However, Python is a growing presence in this space. A number of small open source projects such as MyHDL, FuPy and others represent grassroots, bottoms-up efforts to foster the Python and FPGA movement. Meanwhile, major players like Xilinx with their PYNQ platform are clearly embracing Python's place in the programmable logic realm.

As Python gets closer and closer to "the metal", it makes sense to consider the language as a potential successor to C, SystemC, or OpenCL as a preferred FPGA design entry language for high-level synthesis (HLS)based development.

This talk will provide a brief tour though Python's evolution in the world of hardware design and attempt to make a case for Python as tomorrow's HLS language of choice.

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Approaches for programming an FPGA: an overview

Presented by Jan Kuper

Over the past few years FPGAs became more popular due to reasons such as their suitability as accelerators, their low energy consumption, their predictable timing behaviour in real time applications. However, their programmability still is an issue of great concern, which hinders a smooth introduction of FPGAs in projects where they would have an added value. In fact, the actual usage of an FPGA in a concrete situation requires a time consuming design process, which more often than not causes a delay in the development of the project at hand.

In this presentation we will discuss various methods to program and configure an FPGA, including traditional hardware description languages (VHDL, Verilog), high level synthesis systems based on mainstream imperative programming languages (e.g., C/C++, Java, Python, etc), mainstream methods offering some parallelism (e.g., OpenCL, Matlab/Simulink), and recently published methods based on functional languages (e.g., Bluespec, Chisel, Clash). Relevant questions in this comparison are, a.o., what abstraction mechanisms an approach offers, how well it offers control over the features of an FPGA, what possibilities it offers for formal verification, how easy it is to test and simulate a design.

We will give some examples to illustrate our findings.

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FPGA System Design for Failsafe Interfaces

Presented by Jonny Doin

Failsafe design is a paramount component of today's hyperconnected world. Systems are interconnected in streams of control and data packets, that are at the base of any and all infrastructures via the Internet fabric. Failsafe in this context means for a component to detect when it behaves out of its expected ways, and to contain the failure, in a way that is the least harmful way to the systems downstream, and possibly letting both upstream and downstream systems to have knowledge of the failure. This very general description is what keeps critical infrastructures like Nuclear Power Plants safe and secure. And now it is what is needed to make the IoT hyperconnected world safe and secure also. In this talk we will show how to explore system failsafe cells designed at the least expensive points of a design: the system interfaces. And we will do so using FPGAs, and parallel logic to implement system behavioral observers and failsafe override logic to elevate simple embedded systems to Failsafe components.

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