What the FAQ is an FPGA
Presented by Clive "Max" Maxfield
Presented by Microchip
A lot of people design embedded systems. Some of them are the hardware design engineers who create the boards. Others are the software developers who program the boards. The one thing that most of them have in common (apart from mutual distrust of each other) is that they predominantly use microcontrollers (MCUs) as the primary processing element in their designs.
Most of them have heard of FPGAs, but all they typically know is that these devices can be programmed to perform different functions -- they don't know how. Similarly, most of them have heard about languages like Verilog and VHDL, but all they typically know is that FPGA designers use these languages to capture the design -- they don't know how these hardware description languages (HDLs) differ from programming languages like C/C++.
In this presentation, engineer, writer, and communicator Max The Magnificent (a legend in his own lunchtime) will rend the veils asunder and reveal all. Max says that we will be leaping from topic to topic with the agility of young mountain goats, so he urges attendees to dress appropriately.
PYNQ: Using FPGA to Accelerate Python applications
Presented by Adam Taylor
PYNQ is an open source Python framework from Xilinx which enables Python developers to access the performance provided by programmable logic, traditionally in the realm of electronic engineers. Being able to access programmable logic from Python brings with it acceleration factors of 10x, 100x and beyond to applications. This session will introduce the PYNQ framework, before demonstrating a number of image processing and machine learning applications developed using the PYNQ framework, showcasing not only the performance boost but also the ease of use.
Zynq ® Ultrascale+™ delivers Deterministic Processing for Mixed Criticality Applications in Industrial, Automotive, and Aviation Markets
Presented by Dr. Giulio Corradi
Today's market requirements are forcing increased computational requirements across all embedded applications through the use of multi-core SoCs, while simultaneously requiring the preservation of legacy real-time code often developed decades ago for single core processors. Often, the performance limitations of real-time processors lead designers to consider and use application processors to achieve desired performance at expense of determinism and worst case execution time (WCET). This webinar describes how to use the ARM Cortex® A53 application processor cluster in Zynq® Ultrascale+™ to implement real-time asymmetric multiprocessing (RTAMP). This approach results in improving worst case execution time (WCET) and reducing latency by isolating and partitioning the cluster such that software developed for single cores can be reused. Demand for this solution is has skyrocketed in Industrial, Automotive and Avionics applications because software architects strongly prefer to use an application processing cluster like a set of single cores when executing real time code. Shared resources like the level 2 cache and memory controller guarantee performances on average, however worst case execution time is affected by interference amongst cores when accessing shared caches and memories. The combination of programmable logic technology and coloured lockdown concepts for shared cache management in conjunction with the open-source Jailhouse hypervisor make it possible to use Linux and bare-metal isolated applications running independently in the cluster. The overhead introduced by a hypervisor is also reduced, making the overall approach very lean.