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PYNQ: Using FPGA to Accelerate Python applications

Adam Taylor - Watch Now

PYNQ is an open source Python framework from Xilinx which enables Python developers to access the performance provided by programmable logic, traditionally in the realm of electronic engineers. Being able to access programmable logic from Python brings with it acceleration factors of 10x, 100x and beyond to applications. This session will introduce the PYNQ framework, before demonstrating a number of image processing and machine learning applications developed using the PYNQ framework, showcasing not only the performance boost but also the ease of use.

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riz.s.t
Score: 0 | 1 month ago | no reply

Hello Adam,
Impressive presentation. is it possible to run Tensor Flow or Pytorch models using Pynq ?

Raghu
Score: 0 | 1 month ago | no reply

Thanks Adam for the nice presentation, Is there any way we can interface/ connect to BeagleBone/raspberry pi boards to PYNQ

MrPotter
Score: 1 | 3 months ago | 1 reply

As a system architect, I factor in performance and reliability requirements in my initial planning. I plan for thread safety, system failure modes, performance up front. Where and how does this process (using Pynq) let you plan and predict to meet these kinds of requirements up front?

AdamTaylorCEngFIETSpeaker
Score: 1 | 3 months ago | no reply

It does not really, PYNQ is good for prototyping and risk reduction it may not be suitable for use in high reliability systems

Joao
Score: 1 | 3 months ago | 1 reply

You have talked mainly about PYNQ. But I was wondering if there is an equivalent of Altera, and how they compare.

AdamTaylorCEngFIETSpeaker
Score: 0 | 3 months ago | 1 reply

I am not aware of an Altera / Intel Equivalent I am afraid

Pieter
Score: 1 | 2 months ago | no reply

Thanks for the talk, you convinced me to buy a PYNQ-compatible board to try this out.

Overlay loading and such should also be possible on Altera boards though, so it may be nice to try to port it. Can you tell how far the Python on FPGA SoC board is Xilinx proprietary code or technically limited to Xilinx only ?

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